module multiply(	
			input [15:0] opnum1,
			input [15:0] opnum2,
			input [2:0] enable,
			input  isNeg1,
			input  isNeg2,
			input sysclk,
			input reset,
			input done,
			output reg isNeg,
			output reg [15:0] result1,
			output reg suc
			);
reg [31:0] result;
reg [2:0] state;
reg [2:0] nstate;
reg [4:0] count;
reg [31:0] opnum1_temp;

parameter s_init = 3'b00,s_add = 3'b01,s_shift = 3'b10,s_finish = 3'b11, s_fix =3'b100 ;

initial begin
	nstate=s_init;
end

always @(posedge sysclk) begin
	state = nstate;
end

always @(posedge sysclk) begin
	if (reset) begin
		nstate = s_init;
		suc = 1'b0;
		isNeg = 1'b0;
		count = 5'd0;
		result = 15'b0;
		opnum1_temp=16'b0;
		end
	else begin
		case (state)
			s_init: begin
						if (enable==3'b011) begin
									result = 32'b0;
									count = 5'd0;
									nstate = s_add;
									suc = 1'b0;
									opnum1_temp = opnum1;
						end
						else  begin
							nstate = s_init;
							suc = 1'b0;
						end
					end
			s_add: begin
				if (opnum2[count])
					result = result + opnum1_temp;
					
				nstate = s_shift;
				end
			s_shift: begin
				  opnum1_temp = {opnum1_temp[30:0],1'b0};
				  count = count+1'b1;
					if (count==5'd16) begin
						// nstate = s_finish;
						nstate = s_fix;
					
						end
					else
						nstate = s_add;
				end
			s_fix: begin
					if(result[31:18])
						result = ( ( (result>>1) + (result>>3)+ (result>>7)+ (result>>8)+ (result>>9)+ (result>>10)+ (result>>12)+ (result>>14)+ (result>>15)+ (result>>16)+ (result>>17) ) >>6 );
					else if(result[31:7])
						result = ( ( (result>>1) + (result>>3)+ (result>>7)+ (result>>8)+ (result>>9)+ (result>>10)+ (result>>11) ) >>6 );
				   else
						result = ( ( (result>>1) + (result>>3)+ (result>>6) ) >>6 );
					result1 = result[15:0];
					isNeg = isNeg1^isNeg2;
					suc = 1'b1;
					nstate = s_finish;
				end
			s_finish: begin
				  if (done) begin
					suc = 1'b0;
					nstate = s_init;
					end
				  else nstate = s_finish;
			 	  end
		endcase
	end
end

endmodule
